Semiconductor chips are fabricated on suitable flat substrate wafers, such as GaAs, diamond coated substrates, silicon carbide, silicon wafers, etc. After making the active devices, a series of steps are performed to connect the various devices with highly conducting wiring structures, so they can have communication with each other to perform logic operations. These wiring structures or interconnect structures are essentially a skeletal network of conducting materials, typically metals in a matrix of dielectric materials. In high performance devices and to improve device density and yield, it is imperative to minimize topographic features within the interconnect layers for any given device and across the entire substrate. One common method of forming these high performance interconnect layers is the damascene process.
Multiple types of damascene structures are known, however the single and dual damascene are the most common. In single damascene, each metal or via layer is fabricated in a series of operations, while in dual damascene, a metal level and a via level are fabricated in a single operation. Of these two, the dual damascene step is often preferred because of lower cost and higher device performance.
In the dual damascene process, a suitable substrate with or without devices is coated with a suitable resist layer. The resist layer is imaged to define desirable patterns by lithographic methods on the substrate. Cavities are etched on the patterned substrates typically by reactive ion etching methods, RIE. The patterned substrate is then coated with a suitable barrier/seed layer prior to overfilling the cavities with a suitable metal, typically copper by electro-deposition from a superfilling plating bath chemistry.
During the damascene process, etch-stop layers are formed between the various layers of the semiconductor device to control the profile of the cavities within the dielectric layer and often may serve as a capping layer. In practice, the dielectric constants of the etch-stop materials tend to be higher than that of the bulk dielectric material. For example, the dielectric constant of fluorinated silicon oxide insulator is 3.5, whereas the typical silicon nitride used as an etch-stop layer is between 7 and 9.
However, etch-stop layers require additional processing time and expense to form and remove, the adhesion of the etch-stop to the metal surface is a reliability concern, because they are often the origin of delamination within the substrate. Also, the presence of the high dielectric constant etch-stop increases the effective capacitance of the device, causes higher RC delay, and can cause unwelcomed stray capacitance as well as undesirable scattering in optical devices.